module licore_tb(
  input clk,
  input rst_n
);

  parameter SIM_CYCLES = 1000000;

  wire [31:0] imem_addr;
  wire [31:0] imem_inst;

  wire        dmem_req;
  wire        dmem_rwn;
  wire [1:0]  dmem_size;
  wire [31:0] dmem_addr;
  wire [31:0] dmem_wdata;
  wire        dmem_grant;
  wire [31:0] dmem_rdata;

licore_top#(
  .BOOT_ADDR(32'b0)
) licore_inst (
  .clk(clk),
  .rst_n(rst_n),
  .imem_addr(imem_addr),
  .imem_inst(imem_inst),

  .dmem_req(dmem_req),
  .dmem_rwn(dmem_rwn),
  .dmem_size(dmem_size),
  .dmem_addr(dmem_addr),
  .dmem_wdata(dmem_wdata),
  .dmem_grant(dmem_grant),
  .dmem_rdata(dmem_rdata)
);

inst_rom#(
  .DEPTH(1024)
) irom_inst (
  .imem_addr(imem_addr),
  .imem_data(imem_inst)
);

data_ram#(
  .DEPTH(4096)
) dram_inst (
  .clk(clk),
  .rst_n(rst_n),
  .mem_req(dmem_req),
  .mem_rwn(dmem_rwn),
  .mem_size(dmem_size),
  .mem_addr(dmem_addr),
  .mem_wdata(dmem_wdata),
  .mem_grant(dmem_grant),
  .mem_rdata(dmem_rdata)
);

initial begin
  $display("Load Instructions from file: licore.rom");
  $readmemh("licore.rom", irom_inst.rom);
end

integer i;
always @(posedge clk, negedge rst_n) begin
  if (~rst_n) begin
    i <= 0;
  end else if (i >= SIM_CYCLES) begin
    $finish;
  end else begin
    i <= i + 1;
  end
end

endmodule

